The present invention relates to plasma etch processes used in the manufacture of semiconductor integrated circuits. More specifically, the present invention relates to a system level in situ integrated process for etching layered dielectric structures serving as inter-level dielectric layers.
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors and other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes of the integrated circuits. The increasing level of integration has also resulted in an increase in the number of layers that make up the integrated circuit. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being developed which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past, one common material for inter-level dielectric materials in integrated circuits was undoped silicon dioxide, which has a dielectric constant (k) generally between about 3.9-4.2. In recent years, semiconductor manufacturers have instead been using materials for inter-level insulation layers that have a dielectric constant below that of silicon dioxide. Two such materials that are now commonly used include fluorine-doped silica glass (FSG), which has a k value generally between about 3.4-3.7 and carbon-doped silica glass (SiOC films) which has a k value between about 2.5 and 3.1.
Concurrent with the move to intermetal dielectric layers having a dielectric constant lower than silicon dioxide, many semiconductor manufacturers are using copper rather than aluminum in the formation of their multilevel interconnect structures. Because copper is difficult to etch in a precise pattern, however, the traditional deposition/selective etch process used for forming such interconnects has become disfavored. Accordingly, a process referred to as a dual damascene process, is used by many semiconductor manufacturers to form copper interconnects. In a dual damascene process, one or more blanket intermetal dielectric layers are deposited and then subsequently patterned and etched to define both the interlayer vias and the interconnect lines. Copper or another conductive material is then inlaid into the defined pattern and any excess conductive material is removed from the top of the structure in a planarization process, such as a chemical mechanical polishing (CMP) process.
The etching of the dielectric layer in such a dual damascene process typically includes two separate lithography steps. One step defines the trenches and another the vias. One particular type of dual damascene structure, illustrated in sectioned isometric view, is shown in FIG. 1.
As shown in FIG. 1, a substrate 10 includes a conductive feature 11 in its surface. If substrate 10 already includes a wiring level at its surface, the conductive feature 11 is metallic and may be a previously formed dual damascene metalization. The interconnection between two metallic wiring levels is called a via. Conventionally, the metal forming the metalization has been aluminum and its alloys or tungsten, but many advanced integrated circuits are now being designed with copper metalization. Alternatively, conductive feature 11 may be a doped region in silicon substrate 10, for example, a source or drain. In this case, the interconnection between the silicon layer and a first metalization layer is called a contact. Although the method and technique of the present invention may be beneficially applied to the formation of contacts, the invention is believed to be particularly useful in the formation of vias, particularly copper vias and underlying copper lines 11.
A lower stop layer 12 (sometimes referred to as a barrier layer when deposited over metalization), a lower dielectric layer 14, a middle stop layer 16, and an upper dielectric layer 20 are deposited over substrate 10 and included conductive feature 11. Stop layers 12, 16 have compositions relative to those of dielectric layers 14, 20 such that an etch chemistry is available which effectively etches a vertical hole in the overlying dielectric layer 14, 20 but stops on the stop layer 12, 16. That is, the etch selectively etches the dielectric layer over the stop layer. Alternatively stated, the dielectric etch is selective to the stop material. As mentioned before, more advanced circuits are being designed with the two dielectric layers 14, 20 being composed of a dielectric material having a lower dielectric constant than that of silicon dioxide, such as carbon-doped silica glass. Accordingly, the specific example of the damascene structure described here uses Black Diamond™, which is an SiOC material (sometimes referred to as an SiCOH material), developed by Applied Materials the assignee of the present invention, as the via and trench dielectric layers. Two typical stop or barrier materials for Black Diamond™ are either a silicon carbide (SiC or SiCN) material, such as BloK™ also developed by Applied Materials or silicon nitride (SiN). Black Diamond™ and BloK™ are each trademarks of Applied Materials, the assignee of the present invention.
Black Diamond™ and BloK™ can be grown in successive steps in a single reactor or in separate chambers of the same multichamber system by plasma-enhanced chemical vapor deposition (PECVD) techniques. For example, Black Diamond™ can be grown using PECVD techniques using trimethylsilane (TMS) and molecular oxygen as the process gas. BloK™ can be grown in the same reactor using tetramethylcyclotetrasiloxane (TMCTS) as the silica precursor in the presence of a helium carrier gas. One advantage of BloK™ as a stop and/or barrier layer as opposed to silicon nitride is that BloK™ has a lower k value than silicon nitride. These examples are non-limiting and simply show one advantage of the illustrated vertical structure.
The dual damascene etch structure shown in FIG. 1 is formed in the previously described vertical structure. FIG. 2 is a flowchart illustrating one processing sequence that can be performed to etch the dual damascene structure shown in FIG. 1. As shown in FIG. 2, after all the dual damascene layers 12, 14, 16, 20 are grown in a horizontally unpatterned vertical structure (step 74), a first photoresist layer is deposited over trench dielectric layer 20 and patterned with apertures corresponding to the via holes 18 (step 76). Next, an extended via hole is etched from the top of trench dielectric layer 20 to the top of barrier layer 12 using a multistep etch process that must etch very deeply. This step may etch a very narrow hole (e.g., a hole having a width of 0.1 or 0.13 μm and an aspect ratio of greater than 10:1 for contact etching and between about 4-6:1 for typical interlevel dual damascene applications). This multistep etch process (step 78) is rather demanding and must take the possibility of etch stop into consideration. (Etch stop arises from the fact that the high selectivity of fluorocarbon-based oxide etches to underlying silicon or BloK™ as well as verticality of the sidewalls depend upon a polymer depositing on non-oxide surfaces and on the sidewalls. However, if the etching chemistry is too rich, favoring too much polymer formation, the polymer may bridge the sidewalls and cover the oxide bottom of the developing hole thereby preventing further etching.) Earlier steps in this multistep etch process must etch through both the upper trench dielectric layer and the upper BloK™ etch stop layer while the final step of the process requires good selectivity to underlying lower BloK™ barrier layer 12.
At the completion of multistep etch 78, the first photoresist layer is stripped and a new photoresist layer (not shown in FIG. 1) is deposited over the top of the trench dielectric layer 30 and patterned to the area of the trench 22 (step 80). Next, in a trench etch step (step 82), trench dielectric layer 20 is etched down to middle BloK™ stop layer 16, thereby forming trench 22. After trench etch 82, the photoresist layer is stripped (step 84) in a process that also removes any polymer produced during trench etch 82. Stripping the photoresist in step 84 is sometimes referred to as ashing. Finally, lower BloK™ barrier layer 12, which lies exposed at the bottom of via hole 18, is removed to expose contact or metal layer 11 (step 86).
The result of the above process is that a generally circular via hole 18 is etched through the via dielectric layer 14 and the lower BloK™ barrier layer 12 to reach the underlying conductive feature 11. Multiple such via holes 18 are etched to reach different ones of the conductive features 11. Trench 22 extends along the surface of substrate 10 and is etched through trench dielectric layer 20 and middle BloK™ stop layer 16.
After completion of this dual damascene etch structure, trench 22 and vias 18 are filled with a metal such as copper. One common technique used to fill trench 22 and via 18 with copper is electroplating. Copper may also be deposited in the trench and via areas using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process and/or electroless plating, however. Barrier layers are usually first conformally coated in the hole being filled. A typical barrier for copper includes Ta/TaN. The metal is deposited to a thickness that overfills the trench 22 and also covers a top planar surface 30 of the upper oxide layer 30. Chemical mechanical polishing (CMP) is applied to the top surface of the wafer. CMP removes the relatively soft exposed metal but stops on the relatively hard dielectric layer 20. The result is a horizontal metal interconnect within the trench 22 and multiple vertical metal interconnects (vias) in the via holes 18.
As can be appreciated by those of skill in the art, the dual damascene etch process described above requires differing etch chemistries and etch capabilities for the steps used to etch through the trench dielectric layer, strip the photoresist and etch through the barrier layer (steps 82, 84, 86). Because of the different demands such processes place on substrate etching equipment and limitations in the equipment itself, many integrated circuit (IC) fabrication facilities employ separate pieces of equipment or systems within the fab to perform each step of the above described oxide etch sequence. Such an arrangement of equipment provides for an ex situ etch process because substrates must be transferred within the clean room between the various pieces of equipment. Exposure of the wafers to the air environment during the transfer between vacuum chambers may result in corrosion of the metal features of the partially processed integrated circuit. The well known susceptibility of copper to corrosion in air increases the destructive risk. Also, carbon-based residue that forms on the interior of the reactor chamber over time can redeposit on exposed copper surfaces. Since these carbon based residues can be extremely difficult to remove from copper, their presence can adversely impact upon subsequent formation of electrical contacts to the copper.
Furthermore, such an ex situ process may result in the formation of a polymer at the bottom of the contact or via area 18 that is not easily etched in stop layer open step 86. Thus, many integrated circuit manufactures that employ an ex situ process for steps 82, 84, 86 further perform a wet solvent etch by, e.g., dipping the substrate in an HF solution, between photoresist strip step 84 and stop layer open step 86.
Engineers at Applied Materials, the assignee of the present invention, have developed an integrated dielectric etch process that can be implemented in a single etch chamber thus eliminating the problems associated with exposing the substrate to the ambient during the etch process. One version of this single chamber etch process is described in U.S. application Ser. No. 09/201,590 referred to above. The process described in the Ser. No. 09/201,590 application provides an improvement in both etching results and cost of ownership as compared to previously known ex situ dielectric etch processes. The process also can be satisfactorily used to form dual damascene structures without requiring a wet solvent dip between the photoresist strip and stop layer open steps.
The dual damascene dielectric trench and via etch steps are expected to be some of the primary steps in the fabrication of future advanced integrated circuits. Industry sources predict that the market for these dielectric etch solutions is one of the largest, if not the largest, markets for equipment substrate processing manufacturers. Thus, while the all-in-one single chamber in situ dielectric etch solution described in the above patent application provides a distinct improvement over ex situ processes, alternative methods of performing the dielectric etch steps are desirable.